C:\Documents And Settings\Fredlin\Desktop\Ic Design\Synthesis200301
Frontiers | Design and Analysis of a Resistive Sensor Interface With Phase Noise-Energy-Resolution Scalability for a Time-Based Resistance-to-Digital Converter
D flip-flop(delay flip-flop) Wiki - FPGAkey
A family of low-power truly modular programmable dividers in standard 0.35-/spl mu/m CMOS technology | Semantic Scholar
A 6-GHz dual-modulus prescaler using 180nm SiGe technology | Semantic Scholar
Feedback Loops and Flip-Flops - Learning FPGAs - FPGAkey
Low-Power 71 GHz Static Frequency Divider in SiGe:C HBT Technology
buffer - How to find Setup time and hold time for D flip flop? - Electrical Engineering Stack Exchange
PDF) A High Speed Successive Approximation Pipelined ADC | Pushpak Dagade - Academia.edu
Low Power CMOS 8-Bit Current Steering DAC
A 6-GHz dual-modulus prescaler using 180nm SiGe technology | Semantic Scholar
Electronics | Free Full-Text | A 125 KHz, Single-Stage, Dual-Output Wireless Power Receiver with PSM Modulation
digital logic - Dual edge triggered D flip flip CMOS implementation. Less than 20 transistors - Electrical Engineering Stack Exchange
Active Pixel Sensor CMOS Operating Multi - Sampled in Time Domain | IntechOpen
Nanopower sub-threshold biquadratic cells and its application to portable ECG system - ScienceDirect
Feedback Loops and Flip-Flops - Learning FPGAs - FPGAkey
A 6-GHz dual-modulus prescaler using 180nm SiGe technology | Semantic Scholar
EC1354 VLSI DESIGN - NPR College of Engineering & Technology
A 6-GHz dual-modulus prescaler using 180nm SiGe technology | Semantic Scholar
PDF) Characterization of a 0.35-Micron-Based Analog MPPT IC at Various Process Corners | Febus Cruz - Academia.edu
Retentive True Single Phase Clock 18T Flip-Flop with SVL Technique | SpringerLink
PDF) Design and Analysis of Ultra Low Power True Single Phase Clock CMOS 2/3 Prescaler
A dual pulse-clock double edge triggered flip-flop
