Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
Electronics | Free Full-Text | 40 GHz VCO and Frequency Divider in 28 nm FD-SOI CMOS Technology for Automotive Radar Sensors
Schematics of latch and D flip-flop. (a) Latch. (b) D flip-flop. | Download Scientific Diagram
A Novel Ultra High-Speed Flip-Flop-Based Frequency Divider
Current Mode Logic Divider
A FULLY DIFFERENTIAL HIGH-SPEED LOW VOLTAGE DOUBLE-EDGE TRIGGERED FLIP-FLOP ( DETFF ) | Semantic Scholar
DFF-based CMOS clock divider. | Download Scientific Diagram
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
An active inductor employed CML latch for high speed integrated circuits | SpringerLink
Electronics | Free Full-Text | A High-Speed Low-Power Divide-by-3/4 Prescaler using E-TSPC Logic DFFs
Figure 1 from High speed CML latch using active inductor in 0.18μm CMOS technology | Semantic Scholar
High Speed Digital Blocks
A Dynamic Current Mode D-Flipflop for High Speed Application | Semantic Scholar
KR100969864B1 - Cml type d flip-flop and frequency divide-by-odd number using the same - Google Patents
Design of low-power high-speed dual-modulus frequency divider with improved MOS current mode logic | Semantic Scholar
Design of Low Voltage D-Flip Flop Using MOS Current Mode Logic (MCML) For High Frequency Applications with EDA Tool
Schematic timing diagram of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
High Speed Digital Blocks
Analysis and Design of High-Speed CMOS Frequency Dividers
Electronics | Free Full-Text | A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS
An improved current mode logic latch for high‐speed applications - Kumawat - 2020 - International Journal of Communication Systems - Wiley Online Library
4-bit Counter Using High-Speed Low-Voltage CML D-Flipflops | Semantic Scholar
Figure 1 from High-frequency CML clock dividers in 0.13-/spl mu/m CMOS operating up to 38 GHz | Semantic Scholar
Electronics | Free Full-Text | A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS
Figure 2 from New CML latch structure for high speed prescaler design | Semantic Scholar
Circuit configuration of the CML-type SR-latch circuit a Circuit... | Download Scientific Diagram
Electronics | Free Full-Text | High-Speed Wide-Range True-Single-Phase-Clock CMOS Dual Modulus Prescaler
