KR100969864B1 - Cml type d flip-flop and frequency divide-by-odd number using the same - Google Patents
Figure 5.21 from Cmos Logic and Current Mode Logic 5.1 Introduction | Semantic Scholar
High Speed Digital Blocks
Circuit configuration of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
Help me calculate the device size of CML/SCL latch design and simulate the gain of it | Forum for Electronics
Low Power Rail to Rail D Flip-Flop Using Current Mode Logic Structure
DFF-based CMOS clock divider. | Download Scientific Diagram
A Dynamic Current Mode D-Flipflop for High Speed Application | Semantic Scholar
A Novel Ultra High-Speed Flip-Flop-Based Frequency Divider: Ravindran Mohanavelu and Payam Heydari | PDF
Schematic timing diagram of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
CML based DFF used in 4/5 prescaler block | Download Scientific Diagram
Electronics | Free Full-Text | A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS
Figure 4 from Low power inductor-less CML latch and frequency divider for full-rate 20 Gbps in 28-nm CMOS | Semantic Scholar
Low Power Rail to Rail D Flip-Flop Using Current Mode Logic Structure
Electronics | Free Full-Text | A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS
Figure 1 from Design of low-power high-speed dual-modulus frequency divider with improved MOS current mode logic | Semantic Scholar
CML based DFF combined with NAND function used in 4/5 prescaler block | Download Scientific Diagram
Electronics | Free Full-Text | 40 GHz VCO and Frequency Divider in 28 nm FD-SOI CMOS Technology for Automotive Radar Sensors
Analysis and Design of High-Speed CMOS Frequency Dividers
An improved current mode logic latch for high‐speed applications
Current Mode Logic Divider
KR100682266B1 - Differential output tspc d-type flip flop and frequency divider using it - Google Patents
An active inductor employed CML latch for high speed integrated circuits | SpringerLink
An improved current mode logic latch for high‐speed applications - Kumawat - 2020 - International Journal of Communication Systems - Wiley Online Library
![PDF] New CML latch structure for high speed prescaler design | Semantic Scholar](https://d3i71xaburhd42.cloudfront.net/93868f9ab79d1ff6f718775e3548ec22466130cd/2-Figure2-1.png "PDF] New CML latch structure for high speed prescaler design | Semantic Scholar")