Performance evaluation of the low-voltage CML D-latch topology - ScienceDirect
Design of Low Power and High-Speed Cmos D Flipflop using Supply Voltage Level (SVL) Methods
adding reset function to D Flip FLOP | Forum for Electronics
A Dynamic Current Mode D-Flipflop for High Speed Application
adding reset function to D Flip FLOP | Forum for Electronics
High Speed Digital Blocks
![PDF] New RTD-based set/reset latch IC for high-speed mobile D-flip flops | Semantic Scholar](https://d3i71xaburhd42.cloudfront.net/a9f1b39596e7f08405b62eebe623914a1e5c78d1/2-Figure2-1.png "PDF] New RTD-based set/reset latch IC for high-speed mobile D-flip flops | Semantic Scholar")
PDF] New RTD-based set/reset latch IC for high-speed mobile D-flip flops | Semantic Scholar
Circuit configuration of the CML-type SR-latch circuit a Circuit... | Download Scientific Diagram
PDF) Low-power high-speed performance of current-mode logic D flip-flop topology using negative-differential-resistance devices
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
Electronics | Free Full-Text | 0.5-V Frequency Dividers in Folded MCML Exploiting Forward Body Bias: Analysis and Comparison
Schematic timing diagram of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
An active inductor employed CML latch for high speed integrated circuits | SpringerLink
Help me calculate the device size of CML/SCL latch design and simulate the gain of it | Forum for Electronics
PDF) Resonant Tunneling Diode/HBT D-Flip Flop ICs Using Current Mode Logic-Type Monostable-Bistable Transition Logic Element with Complementary Outputs | Taeho Kim - Academia.edu
Part 01: Proposal and Overview. Dual Modulus Prescaler Using Current Mode Logic Goals 2.5 GHz Operation 8/9 Dual Modulus 0.18uM BSIM 3 Model. - ppt download
MC74VHC74 datasheet - Dual D Flip-Flop with Set and Reset. The MC74VHC74
KR100682266B1 - Differential output tspc d-type flip flop and frequency divider using it - Google Patents
An improved current mode logic latch for high‐speed applications - Kumawat - 2020 - International Journal of Communication Systems - Wiley Online Library
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
PDF) Novel Differential-Mode RTD/HBT MOBILE-based D-Flip Flop IC
Low Power Rail to Rail D Flip-Flop Using Current Mode Logic Structure
PPT - Advantages of Using CMOS PowerPoint Presentation, free download - ID:3409185
Electronics | Free Full-Text | A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS
Figure 5.21 from Cmos Logic and Current Mode Logic 5.1 Introduction | Semantic Scholar
